NVMe over PCIe Transport Specification

Transport

The individual transport specifications allow NVM Express to isolate and independently evolve transports for evolving memory and fabric transports. The NVM Express® (NVMe®) 2.0 specifications define the theory of operations for transports in the NVMe Base specification and the mapping of specific transports to individual specifications.

What is the NVMe over PCIe Transport specification?

The NVMe Base specification was initially created to help define how host software communicates with non-volatile memory across a PCI Express® (PCIe®) bus. The NVMe specifications have grown to include multiple types of transports. The PCIe transport specific information for NVMe technology is now defined in this specification

NVMe architecture works with PCIe technology to transfer data to and from SSDs. NVMe enables rapid storage in computer SSDs and improves over older Hard Disk Drive (HDD) related interfaces such as SATA and SAS.

As of August 2024, NVMe is a set of the following eleven specifications:

  • NVM Express® Base Specification, Revision 2.1
  • Command Set Specifications:
    • NVM Express® NVM Command Set Specification, Revision 1.1
    • NVM Express® NVMe Zoned Namespaces Command Set Specification, Revision 1.2
    • NVM Express® Key Value Command Set Specification, Revision 1.1
    • NVM Express® Subsystem Local Memory Command Set Specification, Revision 1.0
    • NVM Express® Computational Programs Command Set Specification, Revision 1.0
  • Transport Specifications:
    • NVM Express® NVMe over PCIe Transport Specification, Revision 1.1
    • NVM Express® RDMA Transport Specification, Revision 1.1
    • NVM Express® TCP Transport Specification, Revision 1.1
  • NVM Express® NVM Express Management Interface Specification, Revision 2.0
  • NVM Express® NVMe Boot Specification, Revision 1.1

The NVM Express® Base Specification, Revision 2.1 reorganizes sections to distinguish requirements on functionality common to PCIe® and Fabrics implementations, specific to PCIe implementations, and specific to Fabrics implementations.