NVM Express Simulation Verification IP (VIP)

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NVM Express Simulation Verification IP (VIP) 2017-08-23T08:27:57+00:00

Project Description

Cadence’s NVM Express Verification IP is a comprehensive VIP built on top of an industry recognized PCIe VIP. As a configurable full timing bus functional model with complete protocol defined run-time assertions and power callbacks, it allows IP and SOC designers to verify their NVMe designs with confidence. Cadence’s NVMe VIP is simulator and language independent with support for Verilog/VHD/C/System Verilog/Vera/Specman/System C.

http://ip.cadence.com/ipportfolio/verification-ip/simulation-vip/pci-express/nvm-express-simulation-vip

Project Details